1. Field of the Invention
The present invention relates to a method of more rapidly and efficiently checking for errors in components of a high speed mainframe computer. More particularly the present invention relates to a method of examining latch scannable information stored in registers of a processor which are accessible by maintenance personnel at a maintenance controller.
2. Description of the Prior Art
Large mainframe computing systems usually comprise a plurality of cabinets which house major functional components or sections such as instruction processors (IPs), inputs/output processors (IOPs), system support processors (SSPs), main storage units (MSUs) as well as peripheral equipment and their associated controllers and a main maintenance controller (MMC). Such equipment having replicated component interconnected to form a mainframe computing system which may have hundreds of millions of switching elements in the form of logic circuits and registers. These logic circuits, switches and registers are usually operated at or near their maximum operating speeds. Over long periods of use these logic circuits, switches and registers may drift or malfunction and generate errors in the computing system.
It is a known technique to perform parity checks of the data being transferred to and from individual components on a mainframe computing system. When errors are detected in the data being transferred between components and sections within parts of the computing system, the components are isolated and taken off line by reconfiguration of the computing system to permit the source of the error to be found. It is relatively simple to determine that data and/or processing errors are occurring in the various parts of a mainframe computing system, however, the chore of identifying the exact source down to the section, which board and which integrated circuit chip and latch is causing errors is complex and time consuming.
Most modern large mainframe computers have check circuits and scan selectable latches or designators which may be accessed in a manner that permits the state of the latch or designator to be stored in registers or storage components. The information in the stored registers may then be checked and/or displayed. It is known that tens of thousands of such scan selectable latches and designators are built into large mainframe computers. These scan selectable latches and designators are usually arranged in strings and are accessed in a manner which associates each of the latches or designators with a unique identifier denoting the string and the relative position of the latch. The information so accessed may then be grouped in predetermined functional relationships which assist maintenance personnel in analyzing the state of the latches and switches of the computer system and identifying the location of the latch which has an error condition, thus, reducing down time.
A plurality of latches may be displayed in a group referred to as a "pseudo" which consists of an identifying pseudo name and a display of the values of the latches in the pseudo. For example, a register can be displayed under one pseudo name. Associated pseudos may be then grouped into a "panel" of values and displayed together on a maintenance controller oscilloscope. Within each pseudo display, each latch is assigned to a particular bit position in the pseudo word.
Not all latches or designators are singular indicative of a hardware problem. With the increased use of very large scale integration (VLSI) logic circuits, delay considerations related to data propagation times has become increasingly important. The same function or problem may be associated with a plurality of latches or designators, thus, there exists multiple copies (or duplicates) of the same functional latch in the selectable checking circuits. These multiple copies of the same functional latch replicated latch or designator present an entirely new problem concerning how to display them because their presence makes displaying the functional relationship between their unique name or designation and the state of the latch or designator more difficult. Heretofore, it had been preferred to keep multiple copies of the same functional latch on the same panel grouped together so that an error between copies could more easily be detected. As a result of this preference, fewer different functional registers or latches could be placed on a panel. A typical panel may include as few as 10 or as many as 30 unique names or designations depending on the number of columns and rows of information which may be concurrently displayed on, the same panel.
Heretofore, computer designers and circuit designers have applied unique names to latch scan information in a latch scan set such as arithmetic section to indicate the scanned information to be stored in a register for display was derived from a latch scan set somewhere in the arithmetic unit (ALU).
The present invention departs from the prior art practice of displaying all information concerning singular latches and provides a format, method and means for separating the multiple copies from a master functional display of the individual registers and further enhances the ability of service personnel to manually or automatically check the data being displayed on the panel for failure of errors depicted by one or more of the duplicate latches or designators.